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Verilog simulator that transpiles to C++.
One very good thing about this is that it makes it easy to create test cases directly in C++. You just supply inputs and clock the simulation directly in a C++ loop, then read outputs and assert them with assert(). And you can inspect variables by printing them or with GDB. This is infinitely more convenient than doing these IO-type tasks in Verilog itself.
Some simulation examples under verilog.
First install Verilator. On Ubuntu:
sudo apt install verilator
Tested on Verilator 4.038, Ubuntu 22.04.
Run all examples, which have assertions in them:
cd verilator
make run
File structure is for example:
Example list: