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Standard cell library

| nosplit | ↑ parent "Semiconductor physical implementation" | words: 231 | descendant words: 253 | descendants: 1
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Basically what register transfer level compiles to in order to achieve a real chip implementation.
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After this is done, the final step is place and route.
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They can be designed by third parties besides the semiconductor fabrication plants. E.g. Arm Ltd. markets its Artisan Standard Cell Libraries as mentioned e.g. at: https://web.archive.org/web/20211007050341/https://developer.arm.com/ip-products/physical-ip/logic This came from a 2004 acquisition: https://www.eetimes.com/arm-to-acquire-artisan-components-for-913-million/, obviously.
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The standard cell library is typically composed of a bunch of versions of somewhat simple gates, e.g.:
  • AND with 2 inputs
  • AND with 3 inputs
  • AND with 4 inputs
  • OR with 2 inputs
  • OR with 3 inputs
and so on.
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Each of those gates has to be designed by hand as a 3D structure that can be produced in a given fab.
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Simulations are then carried out, and the electric properties of those structures are characterized in a standard way as a bunch of tables of numbers that specify things like:
  • how long it takes for electrons to pass through
  • how much heat it produces
Those are then used in power, performance and area estimates.
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Ancestors

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