Register transfer level (RTL) | 🗖 nosplit | ↑ parent "Computer hardware" | 169, 4, 170

🗖 nosplit | ⇓ toc | ↑ parent "Computer hardware" | Wikipedia | 169, 4, 170

The only two truly relevant RTL languages as of 2020 are: Verilog and VHDL. Everything else compiles to those, because that's all that EDA vendosr support.

🔗

Much like a C compiler abstracts away the CPU assembly to:

increase portability across ISAs
do optimizations that programmers can't feasibly do without going crazy

🔗

Compilers for RTL languages such as Verilog and VHDL abstract away the details of the specific semiconductor technology used for those exact same reasons.

🔗

The compilers essentially compile the RTL languages into a standard cell library.

🔗

Examples of companies that work at this level include:

Intel. Intel also has semiconductor fabrication plants however.
Arm Holdings, which does not have fabs, and is therefore called a "fabless" company.

🔗

Table of contents | 169, 4, 170
- 1. Logic gate | 🔗 link | 🗖 nosplit | ↑ parent "Register transfer level"
- 2. Verilog | 🔗 link | 🗖 nosplit | ↑ parent "Register transfer level"
- 3. VHDL | 0, 1, 1 | 🔗 link | 🗖 nosplit | ↑ parent "Register transfer level"
  - 3.1. GHDL | 1 | 🔗 link | 🗖 nosplit | ↑ parent "VHDL"

🔗

Register transfer level (RTL) | 🗖 nosplit | ↑ parent "Computer hardware" | 169, 4, 170

Incoming links