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Instruction set architecture
(ISA)
...
Area of technology
Information technology
Computer
Computer hardware
Computer hardware component type
Processor (computing)
OurBigBook.com
Words: 6k
Articles: 62
The main interface between the
central processing unit
and
software
.
Table of contents
6k
62
Assembly language
Instruction set architecture
18
2
Assembler
(computing)
Assembly language
1
GNU Assembler
(GNU GAS)
Assembler
Calling convention
Instruction set architecture
List of instruction set architectures
Instruction set architecture
6k
57
One instruction set computer
(OISC)
List of instruction set architectures
ARM architecture family
List of instruction set architectures
174
PowerPC
List of instruction set architectures
RISC-V
List of instruction set architectures
169
10
RISC-V International
(RISC-V Foundation)
RISC-V
RISC-V vendor
RISC-V
41
3
Codasip
RISC-V vendor
SiFive
RISC-V vendor
15
SiPearl
RISC-V vendor
26
RISC-V timer
RISC-V
73
1
riscv/timer.S
RISC-V timer
73
RISC-V priviledged ISA
RISC-V
2
RISC-V MSTATUS register
RISC-V priviledged ISA
1
RISC-V MSTATUS.MIE field
RISC-V MSTATUS register
x86
List of instruction set architectures
6k
41
x86 Paging Tutorial
x86
4k
39
1.
Sample code
x86 Paging Tutorial
2.
Intel manual
x86 Paging Tutorial
3.
Application
x86 Paging Tutorial
4.
Hardware implementation
x86 Paging Tutorial
5.
Segmentation
x86 Paging Tutorial
6.
Example: simplified single-level paging scheme
x86 Paging Tutorial
7
6.1.
Single level paging scheme visualization
Example: simplified single-level paging scheme
6.2.
Single level paging scheme numerical translation example
Example: simplified single-level paging scheme
6.3.
Multiple addresses translate to a single physical address
Example: simplified single-level paging scheme
6.4.
Identity mapping
Example: simplified single-level paging scheme
6.5.
Page faults
Example: simplified single-level paging scheme
6.6.
Page table entries
Example: simplified single-level paging scheme
6.7.
Page size choice
Example: simplified single-level paging scheme
7.
Example: multi-level paging scheme
x86 Paging Tutorial
5
7.1.
The problem with single-level paging
Example: multi-level paging scheme
7.2.
K-ary trees to the rescue
Example: multi-level paging scheme
7.3.
Why not a balanced tree
Example: multi-level paging scheme
7.4.
How the K-ary tree is used in x86
Example: multi-level paging scheme
7.5.
Multi-level paging scheme numerical translation example
Example: multi-level paging scheme
8.
64-bit architectures
x86 Paging Tutorial
9.
PAE
x86 Paging Tutorial
10.
PSE
x86 Paging Tutorial
11.
PAE and PSE page table schemes
x86 Paging Tutorial
12.
TLB
x86 Paging Tutorial
4
12.1.
Basic TLB operation
TLB
12.2.
TLB replacement policy
TLB
12.3.
CAM
TLB
12.4.
Invalidating TLB entries
TLB
13.
Linux kernel usage
x86 Paging Tutorial
5
13.1.
Play with physical addresses in Linux
Linux kernel usage
13.2.
Kernel vs process memory layout
Linux kernel usage
13.3.
Process memory layout
Linux kernel usage
13.4.
Copy-on-write
(COW)
Linux kernel usage
13.5.
Linux source tree
Linux kernel usage
14.
Memory management unit
x86 Paging Tutorial
15.
Second Level Address Translation
x86 Paging Tutorial
16.
Other architectures
x86 Paging Tutorial
1
16.1.
ARM
Other architectures
17.
Bibliography
x86 Paging Tutorial
x86 custom instructions
x86
58
Y86
List of instruction set architectures
15
Ancestors
(8)
Processor (computing)
Computer hardware component type
Computer hardware
Computer
Information technology
Area of technology
Technology
Home
Incoming links
(6)
Assembly language
Google custom silicon
How computers work?
List of instruction set architectures
Memory semantics
x86 Paging Tutorial
Synonyms
(1)
ISA
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