riscv/timer.S

TODO: the interrupt is firing only once:

www.reddit.com/r/RISCV/comments/ov4vhh/timer_interrupt/

Adapted from: danielmangum.com/posts/risc-v-bytes-timer-interrupts/

sudo apt install binutils-riscv64-unknown-elf qemu-system-misc gdb-multiarch
cd riscv
make

Then on shell 1:

qemu-system-riscv64 -machine virt -cpu rv64 -smp 1 -s -S -nographic -bios none -kernel timer.elf

and on shell 2:

gdb-multiarch timer.elf -nh -ex "target remote :1234" -ex 'display /i $pc' -ex 'break *mtrap' -ex 'display *0x2004000' -ex 'display *0x200BFF8'

GDB should break infinitel many times on mtrap as interrupts happen.

riscv/timer.S

/* Adapted from: https://danielmangum.com/posts/risc-v-bytes-timer-interrupts/ */

.option norvc
.section .text
.global _start
_start:
    /* MSTATUS.PRIV = 0 */
    li t0, (0b11 << 7)
    csrs mstatus, t0

    /* MTVEC = mtrap
      Where to jump after each timer interrupt. */
    la t0, mtrap
    csrw mtvec, t0

    /* setup timer */
    /* mtime */
    li t1, 0x200BFF8
    lw t0, 0(t1)
    li t2, 50000
    add t0, t0, t2
    /* mtimecmp */
    li t1, 0x2004000
    sw t0, 0(t1)

    /* MSTATUS.MIE = 1 */
    li t0, (1 << 3)
    csrs mstatus, t0

    /* MIE.MTIE = 1 */
    li t0, (1 << 7)
    csrs mie, t0
spin:
    j spin

mtrap:
    /* setup timer */
    /* mtime */
    li t1, 0x200BFF8
    ld t0, 0(t1)
    li t2, 50000
    add t0, t0, t2
    /* mtimecmp */
    li t1, 0x2004000
    sd t0, 0(t1)

    j spin

riscv/timer.S

 Ancestors (12)