Ciro Santilli
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Place and route
wiki
Electronic design automation phase
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words:
39
Given a bunch of interlinked
standard cell library
elements from the
logic synthesis
step, actually decide where exactly they are going to go on 2D (stacked 2D)
integrated circuit
surface.
Sample output format of place and route would be
GDSII
.
Table of contents
39
Integrated circuit layout
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Place and route
0
GDSII
link
nosplit
Integrated circuit layout
6
Ancestors
Electronic design automation phase
Electronic design automation
Semiconductor device fabrication
Computer hardware
Computer
Information technology
Area of technology
Technology
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Electronic design automation
Standard cell library