37.6.1. Cache coherence
In simple terms, when a certain group of caches of different CPUs are coherent, reads on one core always see the writes previously made by other cores. TODO: is it that strict, or just ordering? TODO what about simultaneous read and writes?
Cache coherence:
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guarantees eventual write propagation
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guarantees a single order of all writes to same location
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no guarantees on when writes propagate
And notably it contrasts that with Memory consistency, which according to them is about ordering requirements on different addresses.
Algorithms to keep the caches of different cores of a system coherent. Only matters for multicore systems.
The main goal of such systems is to reduce the number of messages that have to be sent on the coherency bus, and even more importantly, to memory (which passes first through the coherency bus).
The main software use case example to have in mind is that of multiple threads incrementing an atomic counter as in userland/cpp/atomic/std_atomic.cpp, see also: atomic.cpp. Then, if one processors writes to the cache, other processors have to know about it before they read from that address.
Even if caches are coherent, this is still not enough to avoid data race conditions, because this does not enforce atomicity of read modify write sequences. This is for example shown at: Detailed gem5 analysis of how data races happen.