37.6.1.6. MOSI cache coherence protocol
https://en.wikipedia.org/wiki/MOSI_protocol The critical MSI vs MOSI section was a bit bogus though: https://en.wikipedia.org/w/index.php?title=MOSI_protocol&oldid=895443023 but I edited it :-)
In MSI, it feels wasteful that an MS transaction needs to flush to memory: why do we need to flush right now, since even more caches now have that data? Why not wait until later ant try to gain something from this deferral?
The problem with doing that in MSI, is that not flushing on an MS transaction would force us to every S eviction. So we would end up flushing even after reads!
MOSI solves that by making M move to O instead of S on BusRd. Now, O is the only responsible for the flush back on eviction.
So, in case we had:
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processor 1: M
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processor 2: I then read
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processor 1: write
An MSI cache 1 would do:
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write to main memory, go to S
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BusUpgr, go back to M, 2 back to I
and MOSI would do:
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go to O (no bus traffic)
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BusUpgr, go back to M
This therefore saves one memory write through and its bus traffic.