37.6.1.5. MESI cache coherence protocol
Splits the Shared of MSI cache coherence protocol into a new Exclusive state:
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MESI Exclusive: clean but only present in one cache
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MESI Shared: clean but present in more that one cache
Exclusive is entered from Invalid after a PrRd, but only if the reply came from DRAM (or if we snooped that no one sent the reply to DRAM for us to read it)! If the reply came from another cache, we go directly to shared instead. It is this extra information that allows for the split of S.
This is why the simplified transition diagram shown in many places e.g.: https://upload.wikimedia.org/wikipedia/commons/c/c1/Diagrama_MESI.GIF is not a proper state machine: I can go to either S or E given a PrRd.
The advantage of this over MSI is that when we move from Exclusive to Modified, no invalidate message is required, reducing bus traffic: https://en.wikipedia.org/wiki/MESI_protocol#Advantages_of_MESI_over_MSI
This is a common case on read write modify loops. On MSI, it would:
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first do PrRd
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send BusRd (to move any M to S), get data, and go to Shared
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then PrWr must send BusUpgr to invalidate other Shared and move to M
With MESI:
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the PrRd could go to E instead of S depending on who services it
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if it does go to E, then the PrWr only moves it to M, there is no need to send BusUpgr because we know that no one else is in S
gem5 12c917de54145d2d50260035ba7fa614e25317a3 has two Ruby MESI models implemented: MESI_Two_Level and MESI_Three_Level.