37.5. Hardware threads
Intel name: "Hyperthreading"
gem5 appears to possibly have attempted to implement hardware threads in gem5 syscall emulation mode as mentioned at gem5 syscall emulation --smt.
On fs.py it is not exposed in any in-tree config however, and as pointed by the above issue O3 FS has an assert that prevents it in src/cpu/o3/cpu.cc:
// SMT is not supported in FS mode yet.
assert(this->numThreads == 1);
TODO why only in fs.py? Is there much difference between fs and se from a hyperthreading point of view? Maybe the message is there because as concluded in gem5 O3ThreadContext, registeres for DerivO3CPU are stored in DerivO3CPU itself (FullO3CPU), and therefore there is no way to to currently represent multiple register sets per CPU.
Other CPUs just appear to fail non-gracefully, e.g.:
./run --arch aarch64 --emulator gem5 -- --param 'system.cpu[0].numThreads = 2'
fails with:
fatal: fatal condition interrupts.size() != numThreads occurred: CPU system.cpu has 1 interrupt controllers, but is expecting one per thread (2)