vhdl/literals.vcd
$date
Tue Aug 16 16:02:30 2022
$end
$version
GHDL v0
$end
$timescale
1 fs
$end
$scope module standard $end
$upscope $end
$scope module textio $end
$upscope $end
$scope module std_logic_1164 $end
$upscope $end
$scope module literals_tb $end
$var integer 32 ! my_integer $end
$upscope $end
$enddefinitions $end
#0
b10000000000000000000000000000000 !