vhdl/counter.vcd

$date
  Tue Aug 16 16:02:30 2022
$end
$version
  GHDL v0
$end
$timescale
  1 fs
$end
$scope module standard $end
$upscope $end
$scope module textio $end
$upscope $end
$scope module std_logic_1164 $end
$upscope $end
$scope module common $end
$upscope $end
$scope module numeric_std $end
$upscope $end
$scope module counter_tb $end
$var reg 1 ! rst $end
$var reg 1 " load $end
$var reg 1 # clk $end
$var reg 2 $ data[1:0] $end
$var reg 2 % count[1:0] $end
$scope module counter_0 $end
$var reg 1 & rst $end
$var reg 1 ' clk $end
$var reg 1 ( load $end
$var reg 2 ) data[1:0] $end
$var reg 2 * count[1:0] $end
$var reg 2 + cnt[1:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
0!
1"
0#
b00 $
bUU %
0&
0'
1(
b00 )
bUU *
bUU +
#500000
1#
b00 %
1'
b00 *
b00 +
#1000000
0"
0#
bUU $
0'
0(
bUU )
#1500000
1#
b01 %
1'
b01 *
b01 +
#2000000
0#
0'
#2500000
1#
b10 %
1'
b10 *
b10 +
#3000000
0#
0'
#3500000
1#
b11 %
1'
b11 *
b11 +
#4000000
1"
0#
b10 $
0'
1(
b10 )
#4500000
1#
b10 %
1'
b10 *
b10 +
#5000000
0"
0#
bUU $
0'
0(
bUU )
#5500000
1#
b11 %
1'
b11 *
b11 +
#6000000
0#
0'
#6500000
1#
b00 %
1'
b00 *
b00 +
#7000000
0#
0'
#7500000
1#
b01 %
1'
b01 *
b01 +
#8000000
0#
0'