vhdl/clock.vcd

$date
  Tue Aug 16 16:02:30 2022
$end
$version
  GHDL v0
$end
$timescale
  1 fs
$end
$scope module standard $end
$upscope $end
$scope module textio $end
$upscope $end
$scope module std_logic_1164 $end
$upscope $end
$scope module clock_tb $end
$var reg 1 ! clk $end
$upscope $end
$enddefinitions $end
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