vhdl/adder.vcd

$date
  Tue Aug 16 16:02:30 2022
$end
$version
  GHDL v0
$end
$timescale
  1 fs
$end
$scope module standard $end
$upscope $end
$scope module common $end
$upscope $end
$scope module adder_tb $end
$var reg 1 ! i0 $end
$var reg 1 " i1 $end
$var reg 1 # ci $end
$var reg 1 $ s $end
$var reg 1 % co $end
$scope module adder_0 $end
$var reg 1 & i0 $end
$var reg 1 ' i1 $end
$var reg 1 ( ci $end
$var reg 1 ) s $end
$var reg 1 * co $end
$upscope $end
$upscope $end
$enddefinitions $end
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