verilog/counter_syn.v

/* Generated by Yosys 0.5+ (git sha1 f13e387, gcc 5.3.1-8ubuntu2 -O2 -fstack-protector-strong -fPIC -Os) */

(* src = "counter.v:7" *)
module counter(clock, reset, enable, out);
  (* src = "counter.v:15" *)
  wire [1:0] _00_;
  (* src = "counter.v:20" *)
  wire [31:0] _01_;
  wire [1:0] _02_;
  (* src = "counter.v:9" *)
  input clock;
  (* src = "counter.v:11" *)
  input enable;
  (* src = "counter.v:12" *)
  output [1:0] out;
  reg [1:0] out;
  (* src = "counter.v:10" *)
  input reset;
  assign _02_[0] = enable ? _01_[0] : out[0];
  assign _02_[1] = enable ? _01_[1] : out[1];
  assign _00_[0] = reset ? 1'b0 : _02_[0];
  assign _00_[1] = reset ? 1'b0 : _02_[1];
  (* src = "counter.v:15" *)
  always @(posedge clock)
      out[0] <= _00_[0];
  (* src = "counter.v:15" *)
  always @(posedge clock)
      out[1] <= _00_[1];
  assign _01_[1] = out[1] ^(* src = "<techmap.v>:263" *)  out[0];
  assign _01_[0] = out[0] ^(* src = "<techmap.v>:262" *)  1'b1;
endmodule