24.21.2.2.2. gem5 Request in TimingSimpleCPU
In TimingSimpleCPU, the request gets created per memory read:
Fault
TimingSimpleCPU::initiateMemRead(Addr addr, unsigned size,
Request::Flags flags,
const std::vector<bool>& byte_enable)
{
...
RequestPtr req = std::make_shared<Request>(
addr, size, flags, dataMasterId(), pc, thread->contextId());
and from gem5 functional vs atomic vs timing memory requests and gem5 functional vs atomic vs timing memory requests we remember that initiateMemRead is actually started from the initiateAcc instruction definitions for timing:
Fault LDRWL64_LIT::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
{
...
fault = initiateMemRead(xc, traceData, EA, Mem, memAccessFlags);
From this we see that initiateAcc memory instructions are basically extracting the required information for the request, notably the address EA and flags.