24.21.2.2.1. gem5 Request in AtomicSimpleCPU
In AtomicSimpleCPU, a single packet of each type is kept for the entire CPU, e.g.:
RequestPtr ifetch_req;
and it gets created at construction time:
AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
{
ifetch_req = std::make_shared<Request>();
and then it gets modified for each request:
setupFetchRequest(ifetch_req);
which does:
req->setVirt(fetchPC, sizeof(MachInst), Request::INST_FETCH,
instMasterId(), instAddr);
Virtual to physical address translation done by the CPU stores the physical address:
fault = thread->dtb->translateAtomic(req, thread->getTC(),
BaseTLB::Read);
which eventually calls e.g. on fs with MMU enabled:
Fault
TLB::translateMmuOn(ThreadContext* tc, const RequestPtr &req, Mode mode,
Translation *translation, bool &delay, bool timing,
bool functional, Addr vaddr,
ArmFault::TranMethod tranMethod)
{
req->setPaddr(pa);