24.22.4.6. gem5 event queue TimingSimpleCPU syscall emulation freestanding example analysis with caches and multiple CPUs and Ruby
Now let’s do the exact same we did for gem5 event queue AtomicSimpleCPU syscall emulation freestanding example analysis with caches and multiple CPUs, but with Ruby rather than the classic system and TimingSimpleCPU (atomic does not work with Ruby)
Since we have fully understood coherency in that previous example, it should now be easier to understand what is going on with Ruby:
./run \ --arch aarch64 \ --cli-args '2 10' \ --cpus 3 \ --emulator gem5 \ --trace FmtFlag,DRAM,ExecAll,Ruby \ --userland userland/c/atomic.c \ -- \ --cpu-type TimingSimpleCPU \ --ruby \ ;
Note that now the --trace Cache,XBar
flags have no effect, since Ruby replaces those classic memory model components entirely with the Ruby version, so we enable the Ruby
flag version instead. Note however that this flag is very verbose and produces about 10x more output than the classic memory experiment.
Also remember that ARM’s default Ruby protocol is 'MOESI_CMP_directory'
.
First we note that the output of the experiment is the same:
atomic 20 non-atomic 19
TODO