24.22.4.1.3. AtomicSimpleCPU memory access
It will be interesting to see how AtomicSimpleCPU makes memory access on GDB and to compare that with TimingSimpleCPU.
We assume that the memory access still goes through the CoherentXBar, but instead of generating an event to model delayed response, it must be doing the access directly.
Inside AtomicSimpleCPU::tick, we track ifetch_req and see:
fault = thread->itb->translateAtomic(ifetch_req, thread->getTC(),
BaseTLB::Execute);
and later on after translation the memory is obtained at:
icache_latency = sendPacket(icachePort, &ifetch_pkt);
which sends the packet atomically through the port:
AtomicSimpleCPU::sendPacket(MasterPort &port, const PacketPtr &pkt) {
return port.sendAtomic(pkt);
}
We can compare that with what happen sin TimingSimpleCPU:
thread->itb->translateTiming(ifetch_req, thread->getTC(),
&fetchTranslation, BaseTLB::Execute);
and so there it is: the ITB classes are the same, but there are a separate Atomic and Timing methods!
The timing request is shown further at: sends the packet atomically.
Tested in gem5 b4879ae5b0b6644e6836b0881e4da05c64a6550d.