30.3.2.2.1. ARMV8 aarch64 stack alignment
In ARMv8, the stack can be enforced to 16-byte alignment.
This is why the main way to push things to stack is with 8-byte pair pushes with the ARMv8 aarch64 LDP and STP instructions.
ARMv8 architecture reference manual db C1.3.3 "Load/Store addressing modes" says:
When stack alignment checking is enabled by system software and the base register is the SP, the current stack pointer must be initially quadword aligned, that is aligned to 16 bytes. Misalignment generates a Stack Alignment fault. The offset does not have to be a multiple of 16 bytes unless the specific Load/Store instruction requires this. SP cannot be used as a register offset.
ARMv8 architecture reference manual db C3.2 "Loads and stores" says:
The additional control bits SCTLR_ELx.SA and SCTLR_EL1.SA0 control whether the stack pointer must be quadword aligned when used as a base register. See SP alignment checking on page D1-2164. Using a misaligned stack pointer generates an SP alignment fault exception.
ARMv8 architecture reference manual db D1.8.2 "SP alignment checking" is then the main section.
TODO: what does the ABI say on this? Why don’t I observe faults on QEMU as mentioned at: https://stackoverflow.com/questions/212466/what-is-a-bus-error/31877230#31877230
See also: