30.3.3. ARM LDMIA instruction
Pop values form stack into the register and optionally update the address register.
STMDB is the push version.
Example: userland/arch/arm/ldmia.S
The mnemonics stand for:
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STMDB: STore Multiple Decrement Before
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LDMIA: LoaD Multiple Increment After
Example: userland/arch/arm/push.S
PUSH and POP are just mnemonics STDMDB and LDMIA using the stack pointer SP as address register:
stmdb sp!, reglist ldmia sp!, reglist
The ! indicates that we want to update the register.
The registers are encoded as single bits inside the instruction: each bit represents one register.
As a consequence, the push order is fixed no matter how you write the assembly instruction: there is just not enough space to encode ordering.
AArch64 loses those instructions, likely because it was not possible anymore to encode all registers: https://stackoverflow.com/questions/27941220/push-lr-and-pop-lr-in-arm-arch64 and replaces them with the ARMv8 aarch64 LDP and STP instructions