24.22.4.2.27. TimingSimpleCPU analysis #27
Schedules BaseXBar::Layer<SrcType, DstType>::releaseLayer through:
EventManager::schedule BaseXBar::Layer<SlavePort, MasterPort>::occupyLayer BaseXBar::Layer<SlavePort, MasterPort>::succeededTiming CoherentXBar::recvTimingReq CoherentXBar::CoherentXBarSlavePort::recvTimingReq TimingRequestProtocol::sendReq MasterPort::sendTimingReq TimingSimpleCPU::sendFetch TimingSimpleCPU::FetchTranslation::finish ArmISA::TLB::translateComplete ArmISA::TLB::translateTiming ArmISA::TLB::translateTiming TimingSimpleCPU::fetch TimingSimpleCPU::advanceInst TimingSimpleCPU::completeIfetch TimingSimpleCPU::IcachePort::ITickEvent::process