24.22.4.2.1. TimingSimpleCPU analysis #0
Schedules TimingSimpleCPU::fetch through:
EventManager::schedule TimingSimpleCPU::activateContext SimpleThread::activate Process::initState ArmProcess64::initState ArmLinuxProcess64::initState
This schedules the initial tick, much like for for AtomicSimpleCPU.
This time however, it is not a tick as in AtomicSimpleCPU, but rather a fetch event that gets scheduled for later on, since reading DRAM memory now takes time:
TimingSimpleCPU::activateContext(ThreadID thread_num)
{
DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num);
assert(thread_num < numThreads);
threadInfo[thread_num]->notIdleFraction = 1;
if (_status == BaseSimpleCPU::Idle)
_status = BaseSimpleCPU::Running;
// kick things off by initiating the fetch of the next instruction
if (!fetchEvent.scheduled())
schedule(fetchEvent, clockEdge(Cycles(0)));
By looking at the source, we see that fetchEvent runs TimingSimpleCPU::fetch.
Just like for AtomicSimpleCPU, this call comes from the initState call, which is exposed on SimObject and ultimately comes from Python.