23.9.8.3. gem5 Registers trace format

This flag shows a more detailed register usage than gem5 ExecAll trace format.

For example, if we run in LKMC 0323e81bff1d55b978a4b36b9701570b59b981eb:

./run --arch aarch64 --baremetal userland/arch/aarch64/add.S --emulator gem5 --trace ExecAll,Registers --trace-stdout

then the stdout contains:

  31000: system.cpu A0 T0 : @main_after_prologue    :   movz   x0, #1, #0        : IntAlu :  D=0x0000000000000001  flags=(IsInteger)
  31500: system.cpu.[tid:0]: Setting int reg 34 (34) to 0.
  31500: system.cpu.[tid:0]: Reading int reg 0 (0) as 0x1.
  31500: system.cpu.[tid:0]: Setting int reg 1 (1) to 0x3.
  31500: system.cpu A0 T0 : @main_after_prologue+4    :   add   x1, x0, #2         : IntAlu :  D=0x0000000000000003  flags=(IsInteger)
  32000: system.cpu.[tid:0]: Setting int reg 34 (34) to 0.
  32000: system.cpu.[tid:0]: Reading int reg 1 (1) as 0x3.
  32000: system.cpu.[tid:0]: Reading int reg 31 (34) as 0.
  32000: system.cpu.[tid:0]: Setting int reg 0 (0) to 0x3.

which corresponds to the two following instructions:

mov x0, 1
add x1, x0, 2

TODO that format is either buggy or is very difficult to understand:

  • what is 34? Presumably some flags register?

  • what do the numbers in parenthesis mean at 31 (34)? Presumably some flags register?

  • why is the first instruction setting reg 1 and the second one reg 0, given that the first sets x0 and the second x1?