24.17.1.3. gem5 DerivO3CPU
Generic out-of-order core. "O3" Stands for "Out Of Order"!
Basic documentation on the old gem5 wiki: http://www.m5sim.org/O3CPU
Analogous to MinorCPU, but modelling an out of order core instead of in order.
A commented execution example can be seen at: gem5 event queue DerivO3CPU syscall emulation freestanding example analysis.
The default functional units are described at: gem5 DerivO3CPU default functional units. All default widths are set to 8 instructions, from the config.ini:
[system.cpu] type=DerivO3CPU commitWidth=8 decodeWidth=8 dispatchWidth=8 fetchWidth=8 issueWidth=8 renameWidth=8 squashWidth=8 wbWidth=8
This can be observed for example at: gem5 event queue DerivO3CPU syscall emulation freestanding example analysis: hazardless.
Existing parametrizations:
-
ex5_big: big corresponding toex5_LITTLE, by same author at same time. It description reads:ex5 big core (based on the ARM Cortex-A15)
-
O3_ARM_v7a: implemented by Ronald Dreslinski from the University of Michigan in 2012Not sure why it has v7a in the name, since I believe the CPUs are just the microarchitectural implementation of any ISA, and the v8 hello world did run.
The CLI option is named slightly differently as:
--cpu-type O3_ARM_v7a_3.